Binary Phase Shift Keying BPSK Modulation Demodulation Computer Science Essay

Binary Phase Shift Keying BPSK Modulation Demodulation Computer Science Essay This experiment is based on the Binary Phase Shift Keying (BPSK) modulation/demodulation technique. The aim of the experiment is to gain familiarity with the components of a simple data transmission system, gain experience using an experimental communication system and studying its performance under the influence of white noise and also, to compare experimental results with theoretical deductions. Bandpass modulation, of which BPSK is a type, is a process whereby, a sinusoid usually called a carrier wave, is modulated or have its characteristics changed by a digital pulse baseband signal in other to enable wireless based transmission. In BPSK modulation, the phase of the carrier waveform is shifted to either 0Â ° or 180Â ° by the modulating data signal. To effectively model the transmission channel, the AWGN generator is used which adds the effect of noise to the signal at the receiver in other to properly characterise what obtains in real systems. SNR measurements are taken after the noise is added before the receiver and results of each stage of the experiment are presented. 2.0 RESULTS AND DISCUSSION The results obtained from the experiment and brief discussions are now presented. 2.1 The frequency of the waveform was measured to be 1.493kHz 2.2 The amplitude of the waveform was measured to be 3.608V 2.3 C:Documents and SettingsAGEBNIGADesktopLAB RESULTSPart 2.bmp Fig. 1: Square Waveform from NE555 timer circuit. The timer circuit produces a sequence of ones and zeros which together with the resistors and capacitor, produces a square waveform. It can be observed that the square top and bottom are not perfectly straight but with ripples, this is due to the resonance effect presented by the capacitor. Also, the rising pattern of the top is due to the voltage rise time in the capacitor. 2.4 The frequency of the message sequence is measured to be 374Hz 2.5 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 4 5.bmp Fig. 2: Message sequence at the output of the frequency divider. The SN74LS74 integrated circuit implements a second order frequency divider, 2n (n=2). Hence the frequency of the timer circuit is divided by four. Hence, this is also evident in the frequency of the message sequence in 2.4 above. 2.6 The cut-off frequency of the 2nd order Butterworth low pass filter is given by; The cut-off frequency is the frequency at which the magnitude of the transfer function drops to 0.7071 of its maximum value which represents the point at which the power in the circuit is 3dB less than the maximum value. 2.7 The frequency of the sinusoid at the output of the filter was measured to be 1.328kHz. 2.8 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.Wordpart 8.jpg Fig. 3: Output of the first and second Butterworth LPF. A B A Output of first filter; B Output of second filter The Butterworth lowpass filter is used to generate the sinusoidal carrier required for the baseband signal. The Butterworth filter has a gentle roll-off, has no ripple in the pass or stop band hence, it has a monotonic response. To maximise the smoothness of the sinusoid, we use two of such filters in series. 2.9 The RC highpass filter is used to remove the DC components of the sinusoid (since it will only allow frequencies from the cut off frequency upwards) and convert it into a non-return to zero one. The cut-off frequency is given by: 2.10 The frequency of the modulated signal was measured to be 1.408kHz. 2.11 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 11.bmp Fig. 4: Output of the RC filter and the inverting amplifier circuits. A B A RC filter output B Inverting amplifier output The outputs of the RC filter and the inverting amplifier differ by a phase shift of 180Â °, to fulfil the requirement for BPSK where we need antipodal modulated signals. Since the gain of the inverting amplifier is unity, there is no change to the amplitude of the inverted carrier. 2.12 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 10 12.bmp Fig. 5: BPSK signal at the output of the adder circuit. A The analogue switch produces a 0Â ° shifted sinusoid when the message signal is high (a 1) and a 180Â ° shifted sinusoid when the message signal is low (a 0). The two outputs streams are combined in the adder circuit which has a gain of unity so that no modification is made to the signal amplitude. The result of this is a stream of 1s and 0s represented by the sinusoidal waveform in fig. 5 above. Point A depicts the sudden phase change as the bits changes to connote a transition from a high to a low and vice-versa. If we begin with a 1, then the fig. 4 would represent 10101010. 2.13 The bandwidth of the noise signal is 500kHz. 2.14 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 14.jpg Fig. 6: BPSK signal with white noise. The AWGN channel helps to simulate what can typically obtain in real communication environments and it was observed that in real systems, the signal is not really as elegant as presented in fig. 5 but the addition of noise means the receiver will require some form of intelligence and signal processing in other to correctly detect the transmitted message. 2.15C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 15.jpg Fig. 7: BPSK noisy signal at output of RC lowpass filter. The cut-off frequency of this filter is given by; hence it will cut off signals above 15.92kHz. It was observed that after the application of this filter, the noise level was significantly reduced as evident comparing fig. 6 and 7, since the noise contained a large amount of frequency components higher than 15.92kHz due to its bandwidth of 500kHz. 2.16 The signal at the output of the integrator takes the shape of a sawtooth waveform. This is because integrating a square waveform produces a sawtooth waveform. 2.17 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 16 17.bmp Fig. 8: Output of the integrator circuit. A B The multiplier and integrator circuit represents a matched filter implementation at the receiver. Point A represents the zero point i.e the beginning of a new symbol or bit in this case, when the integrator is re-set. As such, when a 1 changes to a 0, we have a re-set to zero point and the direction of the triangular shape changes to the opposite. Point B is the integration phase proper. It is not smooth due to the effect of noise in the system. Also, the rise is a direct result of the capacitor charging. 2.18 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 18.jpg Fig. 9: Pulse application to integrator. A B A Integrator output; B Reset Pulse As displayed on fig. 8 above, the reset pulse is applied to the integrator at the symbol transition instant which is seen to be the beginning of every half cycle to reset the integrator to zero. 2.19 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 19a.png Fig. 10: The Reference Signal C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.Word19b.jpg Fig. 11: The Sampling Pulse C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 19c.jpg Fig. 12: The Reset Pulse The reference signal is obtained from the SN74LS74 frequency divider of the transmitter thus it is the originally transmitted message sequence. The sampling and reset instances are done at the same time that is at the half cycle. 2.20 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 20.jpg Fig. 13: Output of the Comparator. This is where the original baseband signal is regenerated. From fig. 8, when the output of the integrator is positive, an output voltage of 5 volts is produced at the comparator and when the integrator output is negative, a 0 volt output is obtained. This resulted in fig. 13 above showing the alternating 5 and 0 volts or 1s and 0s which depicts our detected signal. The frequency of the detected signal is 1.419kHz. 2.21 The length of the delayed version of the data symbol produced at the receiver is 1.804ms 2.22 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 21 and 22 Greeen channel 2 yellow channel 1.bmp Fig. 14: The Delayed pulse and Original data signal. A B A- Delayed Pulse; B Original Pulse Comparing the original data signal against the delayed version, it is observed that though they are of the same period, B has longer duration positive half cycle while A compensates with a longer negative half cycle. Also, the time delay between them is about a half cycle. 2.23 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 23 yellow delay green comparator.bmp Fig. 15: Input Signals to the XOR circuit. A B A Delayed original signal; B Detected signal The detected signal B is compared against the delayed version of the original signal A, because B generally, B would have experienced some delay and hence to effectively ascertain if an error occurred, its best to compare it against a delayed original as represented by A. The exclusivity of the circuit lies in the fact that when A B are the same, a 0 will be produced while when they are different denoting an error, a 1 will be produced. 2.24 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 24 green 2 yellow 1.jpgFig. 16: Input Signals to the first NAND gate. A B A Sampling Pulse; B XOR Output A NAND gate will only produce a zero when both inputs are high. Hence a zero is obtained when the sampling instant coincides with a high output from the XOR circuit. 2.25 C:Documents and SettingsAGEBNIGALocal SettingsTemporary Internet FilesContent.WordPart 25 yellow chn1 5v dc green chn2 1st input.png Fig. 17: Input Signals to the second NAND gate. A B C A Input 5Vdc; B Output of first NAND gate; C Zero point Since a NAND gate will produce a high when both inputs are not the same and when they are both 0, a 5V dc (always high or 1) is applied to one of the inputs and the output of the first NAND gate to the other. Hence, at the points where B comes down to zero (C), the output of the NAND gate will record a high which implies an error has occurred. 2.26 To estimate the BER; Where Vs (rms value of signal amplitude) =514mV, Vn (rms value of noise amplitude) = 0-10dB W (AWGN channel bandwidth) = 500kHz T (modulated Signal period) = 656.25ÃŽÂ ¼s SNR received signal to noise ratio BER bit error rate or error probability. Table 1 below presents the values. Table 1: Summary of Results Fig. 18: BER Performance Plot 3.0 CONCLUSION The BER performance plot of fig. 18 shows that the behaviour of the experimental system is within the bounds of predicted theoretical results. For instance, as quoted in the lecture notes, at SNR= 10.4dB, the BER is about 1.510-6. From fig.18 above, a similar point, of SNR=10.3806dB gives a BER of 1.48810-6. Hence confirming the accuracy of the results obtained from the experiment. The plot confirms that as the signal-to-noise ratio increases, the error probability reduces in line with conventional knowledge. In addition, the process of using a baseband signal to modulate the phase of a sinusoid was observed, converting it into a bandpass signal for transmission ease. Also, the use of Additive White Gaussian Noise to simulate the channel provides an insight into what might be expected in a live system environment, under varying degrees of noise exposure. Finally, because the received data sequence will most likely be displaced from its true positions as demonstrated experimentally, the use of a time delayed version of the original transmitted sequence to compare and check for errors was justified.